Identifying Application Performance Limitations Associated with Microarchitecture Design

This paper presents and employs a methodology to analyze application performance with respect to microarchitecture design. As demonstrated by a case study of Sweep3D, this methodology systematically evaluates application performance improvements associated with enhancements to a baseline processor architecture and, as a result, identifies a microarchitecture, derived from the baseline architecture, that embodies acceptable cost/performance tradeoffs while reducing stalls in the microarchitecture. In the process, architectural design choices that limit the application’s performance are recognized and design changes that will enhance the application’s performance are suggested. Design changes identified by the case study increase Sweep3D’s performance by 1.6% to 24%. This methodology builds the framework for defining the application’s performance threshold, which quantifies performance potential that is unattainable due to application characteristics, rather than architectural design choices.